As integrated circuits have become more complex, the individual devices, such as field effect transistors, forming the integrated circuit have become smaller and more closely spaced to each other. Simple shrinkage of device dimensions was not alone sufficient to permit the increased complexity of the circuits; new processing technologies and innovative devices were also required.
An example will illustrate this point. The source and drain regions of a field effect transistor must be separately electrically contacted. This is frequently done by depositing a dielectric layer over the transistor, patterning the dielectric layer to fore windows which expose portions of the source/drain regions, and then depositing metal in the windows. A typical metal is aluminum. However, aluminum tends to diffuse or spike into the silicon substrate. Such diffusion is undesirable. Diffusion barrier layers am deposited between the substrate and the aluminum to prevent the diffusion and spiking. Deposition of the brier layer material into the windows in the patterned dielectric frequently results in poor coverage of the substrate near the bottoms of the windows. Of course, the dielectric windows must be accurately positioned with respect to the source/drain regions.
An innovative design which decreases the alignment accuracy required for the dielectric windows is described in U.S. Pat. Nos. 4,844,776 and 4,922,311 issued to K. -H. Lee, C. -Y. Lu and D Yaney. These patents describe both a device and a method for making the device which is termed a folded extended window field effect transistor and is commonly referred to by the acronym FEWMOS. In an exemplary embodiment, a layer of a conducting material, such as TiN, is blanket deposited after transistor elements, including an insulating layer on top of the gate electrode, are formed. The conducting material is patterned to form window or landing pads which cover at least portions of the source/drain regions. The window pads may be larger than the source/drain regions provided that they do not contact each other on top of the gate electrode; they may also extend onto the field oxide regions adjacent the source/drain regions. Improved tolerance for misalignment is obtained. The window pads act as etch stop layers when the windows in the dielectric are etched thereby preventing etching into the source/drain regions.
Dopants must be put into the substrate to form the source/drain regions. This is frequently done by ion implantation. There are many device characteristics that are enhanced by forming shallow junctions; that is, very shallow source/drain regions. Shallow regions may be difficult to fabricate with ion implantation while at the same time maintaining a smooth surface to avoid junction interface roughness. In one embodiment, FEWMOS teaches the use of a polycide as the window pad layer material. The source/drain regions are formed by a thermal drive out from ion implanted polysilicon. A metal is deposited and a salicide formed. However, salicided polysilicon may lead to junction roughness.